This invention relates generally to high voltage transistors and more particularly concerns a high current, high voltage PMOS transistor which is fabricated in a vertical configuration to increase current handling of the transistor and to reduce silicon area needed to produce the transistor.
PMOS transistors are lateral devices. In high voltage applications, the transistor is designed to withstand high voltages by constructing field plates around the drain and n-well regions. The field plates even out the equipotential field lines to avoid voltage concentrations. To increase current handling capability, the device area of the transistor is increased. Therefore, high voltage, high current transistors require a large area of silicon to accommodate the field plates and large device areas.
FIG. 1 shows a cross-sectional view of a conventional high voltage PMOS device 10. As the conventional PMOS device 10 is a symmetrical, circular device only one-half of the device is shown in FIG. 1. The conventional PMOS device 10 is symmetrical across the centerline C.sub.1. The conventional PMOS device 10 has all the elements of a standard high voltage PMOS device, i.e., a source 12, a gate area 14, a drain 16, an inner field plate 18, and an outer field plate 20.
The drain 16 is the innermost region. Adjacent and immediately outside of the drain 16 is an inner field plate 18. Underneath the inner field plate 18 is a p-pinchoff region 17. Adjacent to and outside of the inner field plate 18 and the p-pinchoff region 17 is the gate area 14. Adjacent to and above the gate area 14 is a gate 13. Adjacent to and outside of the gate area 14 is an n-well connection 19. Adjacent to and outside of the n-well connection 19 is the outer field plate 20. Extending underneath the areas of the drain 16, the p-pinchoff region 17, the gate area 14, the source 12 and past the n-well connection 19 is an n-well 22. The outer field plate 20 provides high voltage capability to the n-well 22. Extending underneath and past the outer field plate 20 and overlapping with the outermost edge of the n-well 22 is a field oxide 26. Extending underneath the field oxide 26 is a n-pinchoff region 24.
To accommodate large voltages and large currents, the conventional high voltage PMOS device 10 is designed to cover a large area. The inner field plate 18 and the outer field plate 20 are used to avoid bunching of equipotential lines which can cause the conventional PMOS device 10 to break down in operation. The field plates 18, 20 are what give the vertical PMOS device 30 its high voltage capability. The outer field plate 20 provides high voltage capability to the n-well 22.
Current flows laterally along line L.sub.1 in the conventional PMOS device 10. The conventional PMOS device 10 is a lateral device since the current flows laterally through the device. To increase the current handling capability of the conventional high voltage PMOS device 10 it is necessary to increase the device area. The result of this is that high voltage, high current transistors require a large area to accommodate the field plates and the current densities.
All of the elements described in the conventional PMOS device 10 are conventional elements made in a conventional manner as is known in the art.
Accordingly, it is the primary aim of the invention to provide a high current, high voltage transistor which uses less silicon area.
Further advantages of the invention will become apparent as the following description proceeds.